1. Field of the Invention
The present invention relates to a circuit for reading memory cells, in particular for reading memory cells of semiconductor memory devices, such as non-volatile memories.
2. Discussion of the Related Art
Memory devices are commonly used to store information (either temporarily or permanently) in a number of applications. In a non-volatile memory device the information is stored permanently, in the sense that the information is preserved even when a power supply is off.
Typically, a non-volatile memory device includes a matrix of memory cells, each one used for storing bits of information. For example, in a flash memory, integrated in a chip of semiconductor material, each memory cell consists of a floating-gate MOS transistor, programmed to different levels by modifying a threshold voltage thereof, which is associated with a corresponding logic value.
The ever increasing request for high density memory sizes and the industrial need of a reduction of the cost for storage bit have led to develop techniques in which a single memory cell is adapted to store more than one bit; such memory cells are then referred to as multilevel, as opposed to two-levels memory cells that are adapted to store a single bit.
In a so-called NOR architecture of the memory matrix, each column of memory cells is coupled to a respective bit line, and each row is coupled to a respective word line. During a reading operation, the word line of an addressed memory cell is properly biased, and a current sunk by the memory cell (cell current) flows through the corresponding bit line. The cell current depends on the memory cell threshold voltage, i.e. on the memory cell's programming level.
A bank of sense amplifiers of the memory device receives the cell current, and the logic value stored in the memory cell is evaluated by comparing the cell current with at least one reference current.
Typically, the reference current is generated using a reference cell, a device structurally identical to the memory cell being read, programmed at a reference level. For example, in the case of a memory cell storing one bit, if the cell current is greater than the reference current, then the memory cell is determined to store a high logic value (‘1’), otherwise it is determined to store a low logic value (‘0’). Differently, for discriminating the logic value stored in a multilevel memory cell, a plurality of reference cells is provided, each one programmed at a respective reference level, for providing a plurality of different reference currents (for example, three reference cells are used, generating three reference currents, necessary for reading a four-level memory cell storing two bits of information).
A known memory cell reading technique, hereinafter shortly referred to as “voltage ramp reading technique”, exploits a biasing voltage having a monotone time pattern. In particular, the waveform of the biasing voltage consists of a ramp, which increases linearly over time with a constant slope. According to the monotone biasing voltage, the cell current and the at least one reference current start to be significant at different times, i.e. when the biasing voltage of the memory cell to be read and of the reference cell(s) reaches the respective threshold voltages. Being the logic values by convention associated with increasing values of the threshold voltage, the temporal order according to which the cell current and the reference current exceed a predefined current value, uniquely identifies the logic value stored in the memory cell. In this way, the precision of the reading operation is significantly improved, especially for multilevel memory cells, and made independent of most external factors.
Before an evaluation phase of the reading operation, a phase of pre-charge of the bit lines to a predetermined potential is required, for charging stray capacitances intrinsically associated therewith. In fact, a current flowing through the bit lines causes the charging of the associated stray capacitances, and, accordingly, a corresponding transient is required before the bit line voltages and currents reach a steady value. Thus, for avoiding an incorrect reading performed during this transient, it is necessary to guarantee that the bit line charging is completed, before performing an evaluation on the logic value stored in the memory cell accessed for reading. Regretfully, the length of this transient depends on a number of factors, such as the operating temperature, the value of a supply voltage of the memory device, and statistical variations of parameters whose values are affected by the manufacturing process.
In other words, establishing a precise duration of the pre-charge phase is difficult, because it depends on many factors; on the other hand, it is very important to ensure that the evaluation phase starts only when the pre-charge phase is really completed, and the bit-line potential has stabilized, in each condition of temperature and of supply voltage for each memory cell in the semiconductor chip. The problem is particularly critical when the voltage ramp reading technique is applied.
However, a dead time between the actual completion of the pre-charge phase and the start of the evaluation phase impacts on the memory device access time, increasing the time actually required for a reading operation: this contrasts with the demand for memory devices featuring faster and faster reading operations.
In view of the state of the art outlined in the foregoing, one of the problems that the Applicant has faced has been how to provide a circuit for reading memory cells which allows optimizing the duration of a reading operation in each condition of operating temperature, supply voltage and manufacturing process parameters.